1. Technical Field
This invention generally relates to the testing of integrated circuits, and more specifically relates to a method for testing interconnections between integrated circuits in a manner that avoids signal contention.
2. Background Art
The proliferation of modern electronics into our everyday life is due in large part to the existence, functionality and relatively low cost of advanced integrated circuits. As technology moves ahead, the sophistication of electronic systems increases. An important aspect of manufacturing an advanced electronic system is the ability to thoroughly test the components and subassemblies in the system. Many semiconductor manufacturers have provided various built-in self-test circuits on-chip to help to test the functionality of individual integrated circuits located on the chip. The testability of semiconductors was enhanced with the development of boundary-scan testing, as disclosed in IEEE Standard 1149.1 "Standard Test Access Port and Boundary Scan Architecture." Boundary scan testing allows an integrated circuit to be tested by placing shift registers between functional circuitry and input/output pins when the device is placed in test mode. Test data is typically serially scanned into the shift registers to drive certain inputs, clocks are applied, results are captured, and the resultant outputs are determined by shifting the data out of the registers. The serial shift register elements that make up the boundary scan circuitry is known as a scan chain, because test data may be shifted or "scanned" into or out of the daisy-chained boundary scan registers.
In addition to testing the circuitry on a particular integrated circuit, more recent efforts have also recognized the need to test the interconnections between integrated circuits on an electronic assembly. Testing an electronic assembly, such as a printed wiring board or a system that contains multiple printed wiring boards, is difficult using traditional testing techniques. With the increasing popularity of surface mount technology, feature sizes of printed wiring boards have decreased significantly, making it increasingly difficult for automatic test equipment to contact device pins. In addition, multi-chip module technology is gaining widespread acceptance. Many connections within an multi-chip module are not available for contact to an external tester. For these, and many other reasons, testing of electronic assemblies by use of the IEEE 1149.1 boundary scan standard has become very popular. The 1149.1 standard provides a standardized methodology for applying test patterns without the need for a test fixture to contact the functional pins of integrated circuits mounted on the printed wiring board.
Interconnections on an electronic assembly may be tested using boundary scan testing by shifting in appropriate test data into the scan chain, by pulsing one or more clocks to apply the test pattern and capture data, and by shifting the results data out of the boundary scan chain. In a typical electronic assembly, more than one integrated circuit may be able to drive a given net. Lets assume that two integrated circuits may drive the same net. The test vectors will be constructed and checked in a way that assures that no test vector will cause both drivers to drive the nets to opposite states at the same time. However, skew in signal lines and propagation delays may result in short-term contention when making the transition between test patterns. For example, if one integrated circuit drives a net high during one test vector, and a different integrated circuit drives the same net low during the following test vector, it is possible that both drivers will be driving the net for a short time during the transition. This possibility becomes more pronounced when interconnected integrated circuits are on different scan chains that must work together to test the interconnections.
Very short periods of contention would probably not significantly reduce the life of an integrated circuit. Thus, if interconnect testing were performed as a one-time manufacturing test, this contention problem would probably not warrant any great concern. However, more and more systems are performing interconnect testing as part of a built-in self-test procedure each time the system is powered up or reset. Subjecting the integrated circuits to repeated contention may significantly reduce the lifetimes of the integrated circuits. Without a method for avoiding contention during boundary scan testing, the life of the tested integrated circuits will be cut short.